I2C (Inter-Integrated Circuit)

Resources

• Interrupt - I2C in a Nutshell
• USART, UART, RS232, USB, SPI, I2C, TTL, etc. what are all of these and how do they relate to each other?

Notes

• I²C is a synchronous, multi-controller/multi-target, packet-switched, single-ended, serial communication bus.
• It uses two bidirectional open-collector or open-drain lines:
  • Serial DAta line (SDA)
  • Serial Clock Line (SCL)
• Common I2C bus speeds are the 100 kbit/s standard mode and the 400 kbit/s fast mode.
• Every device its assigned a 7-bit address.
  • It supports up to 127 devices on a bus with only two pins.
• The bus has two roles for nodes, as master or as slave:
  • Controller (master) node: Node that generates the clock and initiates communication with targets.
  • Target (slave) node: Node that receives the clock and responds when addressed by the controller.
• You can also use multi-master architecture
• The value of the SDA line while the SCL line is high is the value of the transmitted bit.
• Every I2C command starts with a START condition and ends with a STOP condition.
  • To send a START, an I2C master must pull the SDA line low while the SCL line is high. After a START condition, the I2C master must pull the SCL line low and start the clock.
  • To send a STOP, an I2C master releases the SDA line to high while the SCL line is high.

For example, this is 0xC9 over I2C: While the SCL line is high, SDA goes low. Then the clock starts. The 8-byte value is transmitted and then, while the SCL is high, SDA goes high.

• A common pattern is to send a write followed by a read. For example, many devices expose several registers that can be read/written by first sending the register address to the device in with a write command.
• The I2C protocol specifies that every byte sent must be acknowledged by the receiver. This is implemented with a single bit: 0 for ACK and 1 for NACK. At the end of every byte, the transmitter releases the SDA line, and on the next clock cycle the receiver must pull the line low to acklowledged the byte.
• When the line remains high during the next clock cycle, it is considered a NACK.

Serial Peripheral Interface (SPI)

• SPI is a synchronous serial communication interface specification used for short-distance communication.
• The SPI bus can operate with a single master device and with one or more slave devices.