Instruction Set Architecture (ISA)

An ISA defines the supported instructions, data types, registers, the hardware support for managing main memory, fundamental features (such as the memory consistency, addressing modes, virtual memory), and the input/output model of a family of implementations of the ISA.
There are 2 main types:
- Complex Instruction Set Computer (CISC): Has many specialized instructions, some of which may only be rarely used in practical programs.
- Reduced Instruction Set Computer (RISC): Simplifies the processor by efficiently implementing only the instructions that are frequently used in programs, while the less common operations are implemented as subroutines, having their resulting additional processor execution time offset by infrequent use.
Parts of ISAs:
- General Purpose Registers: Used in most ALU and branch operations
- Program counter: A processor register that indicates where a computer is in its program sequence.
- Stack pointer: A stack register is a computer central processor register whose purpose is to keep track of a call stack.
- Stack Frame: Part of the stack where local variables, caller and calee saved registers, in/out arguments are store.,

x86

x86 is a family of complex instruction set computer (CISC) instruction set architectures initially developed by Intel based on the Intel 8086 microprocessor and its 8088 variant.
Intel and AMD are the current designers for x86

Advanced RISC Machines is a family of reduced instruction set computer (RISC) instruction set architectures for computer processors, configured for various environments.
Arm Ltd. develops the architecture and licenses it to other companies, who design their own products that implement one or more of those architectures, including system on a chip (SoC) and system on module (SoM) designs, that incorporate different components such as memory, interfaces, and radios. It also designs cores that implement these instruction set architectures and licenses these designs to many companies that incorporate those core designs into their own products.

RISC-V is an open standard instruction set architecture (ISA) that began in 2010 and is based on established reduced instruction set computer (RISC) principles.
Unlike most other ISA designs, RISC-V is provided under open source licenses that do not require fees to use.
RISC-V has a modular design, consisting of alternative base parts, with added optional extensions. The ISA base and its extensions are developed in a collective effort between industry, the research community and educational institutions. The base specifies instructions (and their encoding), control flow, registers (and their sizes), memory and addressing, logic (i.e., integer) manipulation, and ancillaries. The base alone can implement a simplified general-purpose computer, with full software support, including a general-purpose compiler.
- The standard extensions are specified to work with all of the standard bases, and with each other without conflict.

The Xtensa architecture offers a user-customizable instruction set through automated customization tools that can extend the Xtensa base instruction set, including SIMD instructions, new register files.
The Xtensa instruction set is a 32-bit architecture with a compact 16- and 24-bit instruction set. The base instruction set has 82 RISC instructions and includes a 32-bit ALU, 16 general-purpose 32-bit registers, and one special-purpose register.